The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2000

Filed:

Apr. 07, 1999
Applicant:
Inventors:

Wan Yih Lien, Hsinchu, TW;

Kung Linliu, Hsinchu, TW;

Meng-Jaw Cherng, Hsinchu Hsien, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438253 ; 438381 ; 438393 ; 438396 ; 438257 ; 257296 ; 257300 ; 257306 ; 257379 ;
Abstract

A method for forming a DRAM cell of a DRAM circuit is disclosed. The DRAM circuit includes a periphery region and a cell region. The DRAM cell is in the cell region and comprises an access transistor and a capacitor. The access transistor has a gate, a source, and a drain. The periphery region includes a plurality of gates. The method comprises the deposition of a silicon oxynitride layer over the gates, the silicon oxynitride layer acting as a bottom anti-reflection coating. That portion of the silicon oxynitride layer that lies over the DRAM cell is removed. A landing pad is formed over the source of the access transistor and a bitline pad is formed over the drain of the transistor. Next, a first oxide layer is formed over the landing pad and the bitline pad. A capacitor is formed over the landing pad and a second oxide layer is formed over the capacitor. Finally, metal contacts are formed to at least one of the gates in the periphery region using the silicon oxynitride layer as a buffer layer to prevent substrate loss or overetching.


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