The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 1999

Filed:

Mar. 13, 1997
Applicant:
Inventors:

Atsuo Fushida, Kanagawa, JP;

Kenichi Goto, Kanagawa, JP;

Tatsuya Yamazaki, Kanagawa, JP;

Takae Sukegawa, Kanagawa, JP;

Masataka Kase, Kanagawa, JP;

Takashi Sakuma, Kanagawa, JP;

Keisuke Okazaki, Kanagawa, JP;

Yuzuru Ota, Kanagawa, JP;

Hideo Takagi, Kanagawa, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438584 ; 438592 ; 438597 ; 438620 ;
Abstract

A manufacturing method of a semiconductor device of the present invention comprises the steps of forming an amorphous layer on an upper layer of the impurity diffusion layer made of silicon by virtue of ion-implantation, forming a cobalt film on the impurity diffusion layer, forming a cobalt silicide layer made of Co.sub.2 Si or CoSi on an upper layer of the amorphous layer at a low temperature by reacting the cobalt film to silicon in the impurity diffusion layer in virtue of first annealing, then removing the cobalt film which has not reacted, and changing Co.sub.2 Si or CoSi constituting the cobalt silicide layer into CoSi.sub.2 to have low resistance and also rendering the cobalt silicide layer to enter into a depth identical to or deeper than an initial depth of the amorphous layer in virtue of second annealing.


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