Method of fabricating a fin/cavity capacitor structure for dram cell

Abstract

A DRAM is formed by providing a transfer FET, providing an elevated structure over and adjacent to the transfer FET and then forming a cavity above one of the source/drain regions of the transfer FET. The cavity is filled with a conductor to define in part a lower electrode of a charge storage capacitor. Portions of the cavity are then removed to expose additional charge storage surfaces for the lower electrode of the charge storage capacitor. The elevated structure includes a thick, planarized insulating layer provided over the transfer FET. A cavity is formed by providing an etching mask over the thick, planarized insulating layer with an opening positioned over the first source/drain. Etching is performed to remove a portion of the second insulating layer. A thick polysilicon layer is provided to fill the cavity and then the second, thick polysilicon layer is patterned to laterally define the lower capacitor electrode, preferably leaving portions of the second polysilicon layer extending above the stepped opening and onto surrounding portions of the second insulating layer. The second insulating layer is then removed to expose additional surfaces of the lower capacitor electrode for charge storage. Processing continues to provide a capacitor dielectric layer, an upper capacitor electrode and a bit line contact to complete the DRAM.