The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 1999
Filed:
Apr. 24, 1997
Kenneth Edward Beilstein, Jr, Essex Junction, VT (US);
Claude Louis Bertin, South Burlington, VT (US);
Dennis Charles Dubois, Salt Point, NY (US);
Wayne John Howell, Williston, VT (US);
Gordon Arthur Kelley, Jr, Essex Junction, VT (US);
Christopher Paul Miller, Underhill, VT (US);
David Jacob Perlman, Wappingers Falls, NY (US);
Gustav Schrottke, Austin, TX (US);
Edmund Juris Sprogis, Underhill, VT (US);
Jody John VanHorn, Underhill, VT (US);
International Business Machine Corporation, Armonk, NY (US);
Abstract
Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.