Power mosfet device manufactured with simplified fabrication processes

Abstract

This invention discloses a MOSFET device in a semiconductor chip with a top surface and a bottom surface. The MOSFET device includes a drain region, doped with impurities of a first conductivity type, formed in the semiconductor chip near the bottom surface. The MOSFET device further includes a vertical pn-junction region, which includes a lower-outer body region, doped with impurities of a second conductivity type, formed on top of the drain region. The pn-junction region further includes a source region, doped with impurities of the first conductivity type, formed on top of the lower-outer body region wherein the lower-outer body region defining a channel region extending from the source region to the drain region near the top surface. The MOSFET device further includes a gate formed on top of the channel region on the top surface. The gate includes a thin insulative bottom layer for insulating from the channel region. The gate is provided for applying a voltage thereon for controlling a current flowing from the source region to the drain region via the channel region. The MOSFET device further includes a deep heavily doped body-dopant region disposed immediately below the source region in the lower-outer body region. It is implanted with a higher concentration of dopant than the lower-outer body region whereby a device ruggedness of the MOSFET device is improved. The deep heavily-doped body-dopant region having a body-dopant concentration profile defined by a diffusion of the body-dopant from an implant depth about twice as that of a source implant-depth whereby the deep heavily-doped body dopant region is kept at a distance away from the channel region.