The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 1999
Filed:
Nov. 25, 1997
Jun Murata, Kunitachi, JP;
Yoshitaka Tadaki, Palo Alto, CA (US);
Hiroko Kaneko, Hamura-machi, JP;
Toshihiro Sekiguchi, Ohme, JP;
Hiroyuki Uchiyama, Fuchuu, JP;
Hisashi Nakamura, Ohme, JP;
Toshio Maeda, Ohme, JP;
Osamu Kasahara, Hinode-machi, JP;
Hiromichi Enami, Tachikawa, JP;
Atsushi Ogishima, Koganei, JP;
Masaki Nagao, Koganei, JP;
Michimasa Funabashi, Tachikawa, JP;
Yasuo Kiguchi, Kokubunji, JP;
Masayuki Kojima, Kokubunji, JP;
Atsuyoshi Koike, Kokubunji, JP;
Hiroyuki Miyazawa, Kodaira, JP;
Masato Sadaoka, Koganei, JP;
Kazuya Kadota, Hinode-machi, JP;
Tadashi Chikahara, Fuchuu, JP;
Kazuo Nojiri, Higashimurayama, JP;
Yutaka Kobayashi, Katsuta, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.