The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 1999
Filed:
Feb. 20, 1998
Soichiro Arai, Kawasaki, JP;
Kenichi Miyazawa, Kawasaki, JP;
Hidefumi Yabara, Kawasaki, JP;
Hiroshi Yasuda, Kawasaki, JP;
Takayuki Nakatani, Tokyo, JP;
Fujitsu Limited, Kawasaki, JP;
Advantest Corporation, Tokyo, JP;
Abstract
Adjusting variable delay circuit 311, receiving signal S1, is connected to the input of drive circuit 312. A time point t1, when the output potential of drive circuit 312 traverses reference potential VA between the potential Va of traveling wave V1F of the output potential and 0 V, is detected by comparator 52 for detecting the front edge of V1F, detecting variable delay circuit 50 for delaying signal S1 and D flip-flop 51 for holding the output of comparator 52 at the timing of front edge of the signal outputted from delay circuit 50. A time point t2, when the output potential of drive circuit 312 traverses reference potential VB between the superimposed potential of traveling wave V1F and reflected wave V1B and VA, is detected by comparator 62 for detecting the front edge of V1B, detecting variable delay circuit 60 for delaying signal S1 and D flip-flop 61 for holding the output of comparator 62 at the timing of front edge of the signal outputted from delay circuit 60. The delay time of adjusting variable delay circuit 311 is set so that value {t1+(t2-t1)/2} becomes substantially same as to all the output potentials of drive circuit 31 and so on.