The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 1999
Filed:
Feb. 21, 1997
Amitava Chatterjee, Plano, TX (US);
Theodore W Houston, Richardson, TX (US);
Ih-Chin Chen, Richardson, TX (US);
Agerico L Esquirel, Dallas, TX (US);
Somnath Nag, Plano, TX (US);
Iqbal Ali, Plano, TX (US);
Keith A Joyner, Richardson, TX (US);
Yin Hu, Plano, TX (US);
Jeffrey Alan McKee, Grapevine, TX (US);
Peter Stewart McAnally, McKinney, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to 'dishing' that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.