Physical design automation system and process for designing integrated

Abstract

A process for implementation on a programmed digital computer includes providing a placement of clusters of cells which are assigned to regions on an integrated circuit chip, and combining the regions to form region groups. The region groups collectively constitute a 'jiggle' which resembles a sieve. The clusters in each region group are re-assigned to the regions in the region group. The regions are recombined to form different region groups (a different jiggle), and the clusters in each different region group are re-assigned to the regions in the different region group. These steps are repeated using at least two, preferably four different jiggles, until an end criterion is reached. Then, the regions and clusters are hierarchically subdivided, and the process is repeated for each hierarchical level until the clusters have been reduced to individual cells. The regions of the region groups at each level are contiguous, and the region groups overlap, such that a cluster can be moved from any region to any other region on the chip by sufficient repetition of the assignment step using alternating jiggles.