The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 1998

Filed:

Apr. 13, 1998
Applicant:
Inventors:

James Wu, Tze-Kuan, TW;

Yu-Hua Lee, Hsinchu, TW;

Jenn Ming Huang, Hsin-chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438396 ; 438239 ; 438242 ; 438253 ; 438387 ;
Abstract

A method of forming a capacitor for DRAM or other circuits is described which avoids the problem of weak spots or gaps forming between a polysilicon contact plug and the first capacitor plate. A layer of first dielectric is formed on a substrate, A layer of second dielectric is formed on the layer of first dielectric. A layer of third dielectric is formed on the layer of second dielectric. A first hole is formed in the first, second, and third dielectrics exposing a contact region of the substrate. The first hole is then filled with a protective material and a second hole is formed in the layer of third dielectric using the layer of second dielectric as an etch stop. The first hole lies within the periphery of the second hole. The protective material prevents re-deposition of the third dielectric. The remaining protective material is then removed and a layer of conducting material is formed on the top surface of the layer of third dielectric, the sidewalls of the second hole, the sidewalls of the first hole, and the contact region of the substrate thereby forming a first capacitor plate.


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