The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 1998

Filed:

Jul. 29, 1996
Applicant:
Inventors:

Nitin V Sarangdhar, Portland, OR (US);

Gurbir Singh, Portland, OR (US);

Konrad Lai, Aloha, OR (US);

Stephen S Pawlowski, Beaverton, OR (US);

Peter D MacWilliams, Aloha, OR (US);

Michael W Rhodehamel, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395406 ; 395561 ; 395468 ; 395473 ;
Abstract

A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.


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Sarangdhar, Nitin. (1998). Highly pipelined bus architecture (U.S. Patent No. 5796977). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5796977

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