Plasma damage monitor

Abstract

A test structure is described which indicates the occurrence of plasma damage resulting from back-end-of-line processing of integrated circuits. The structure consists of a MOSFET which is surrounded by a conductive shield grounded to the substrate silicon along its base perimeter. The walls of the shield are formed from the sundry levels of conductive layers applied during the integrated circuit interconnection metallization beginning with contact metallurgy which is connected to a diffusion within the substrate. This diffusion is formed within a trench in field oxide surrounding the MOSFET and is of the same conductive type as the substrate material. The top conductive plate of the test structure is formed from a selected metallization layer of the integrated circuit. By forming test structures with top conductive plates formed from two different metallization levels, the plasma damage incurred during the intervening processing steps can be uniquely determined. The test structures may be formed within the wafer saw-kerf area or within wafer test sites. Testing is accomplished by measuring shifts in threshold voltage and drive current before and after gate current stressing. Differences in these shifts from one metallization level to another indicate damage in the MOSFETs gate region has occurred during the processing steps which lie between the depositions of the top conductive plates of the two shields.