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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 5766992 B1

PDFFull Text
Date of Patent:
Jun. 16, 1998

Filed:

Apr. 11, 1997

Process for integrating a mosfet device, using silicon nitride spacers

Applicant:
Inventors:

Chen Cheng Chou, Taichung, TW;

Jenn Tsao, Taipei, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company Ltd., Hsin-Chu, TW;

Attorneys:

Saile; George O.

Ackerman; Stephen B.

Primary Examiner:

Chandra Chaudhari

Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438241 ; 438595 ;
Abstract

A semiconductor fabrication process, allowing integration of MOSFET devices, and capacitor structures, on a single semiconductor chip, has been developed. The process integration features the use of a MOSFET device, fabricated using a self-aligned contact structure, allowing a reduction in the source and drain area needed for contact. Silicon nitride spacers, used on the sides of the polysilicon gate electrode, protect the polysilicon gate structure, during the opening of a self-aligned contact hole.

Find Patent Forward Citations

Chou, Chen. (1998). Process for integrating a mosfet device, using silicon nitride spacers (U.S. Patent No. 5766992). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5766992

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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