The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 1997
Filed:
Jul. 25, 1994
Satoshi Oguchi, Ohme, JP;
Masamichi Ishihara, Hamura-machi, JP;
Kazuya Ito, Hamura-machi, JP;
Gen Murakami, Tama, JP;
Ichiro Anjoh, Koganei, JP;
Toshiyuki Sakuta, Ohme, JP;
Yasunori Yamaguchi, Ohme, JP;
Yasuhiro Kasama, Tokyo, JP;
Tetsu Udagawa, Iruma, JP;
Eiji Miyamoto, Tokyo, JP;
Youichi Matsuno, Koganei, JP;
Hiroshi Satoh, Kodaira, JP;
Atsusi Nozoe, Ohme, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.