The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 1997

Filed:

Sep. 13, 1995
Applicant:
Inventors:

Makoto Yoshimi, Tokyo, JP;

Satoshi Inaba, Tokyo, JP;

Atsushi Murakoshi, Tokyo, JP;

Mamoru Terauchi, Tokyo, JP;

Naoyuki Shigyo, Tokyo, JP;

Yoshiaki Matsushita, Tokyo, JP;

Masami Aoki, Tokyo, JP;

Takeshi Hamamoto, Tokyo, JP;

Yutaka Ishibashi, Tokyo, JP;

Tohru Ozaki, Tokyo, JP;

Hitomi Kawaguchiya, Tokyo, JP;

Kazuya Matsuzawa, Tokyo, JP;

Osamu Arisumi, Tokyo, JP;

Akira Nishiyama, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257192 ; 257 66 ; 257347 ; 257616 ;
Abstract

A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.


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