The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 1997
Filed:
Jan. 31, 1994
Dah Wen Tsang, Bend, OR (US);
Dumitru Sdrulla, Bend, OR (US);
Douglas A Pike, Jr, Bend, OR (US);
Theodore O Meyer, Austin, TX (US);
John W Mosier, II, deceased, late of Bend, OR (US);
Advanced Power Technology, Inc., Bend, OR (US);
Abstract
A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (430) on surface (28) patterns areas (446) as stripes or a matrix, and protected areas. Undercut sidewalls (444) of thickness (452), with protruding rims (447), contact the sides of layer (434'). Trench (450) in areas (446) has silicon sidewalls aligned to oxide sidewall (447) and extending depthwise through P-body layer (26) to depth (456). Gate oxide (460) is formed on the trench walls and gate polysilicon (462) refills trench (450) to a level (464) near surface (28) demarcated by the undercut sidewall rims (447). Oxide (468) between spacers (444) covers polysilicon (462). Removing layer (430) exposes surface (28') between the sidewalls (444). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to inner side faces of sidewalls (444). Trench (80) defines vertically-oriented source and body layers (86, 90) stacked along oxide layer (460) to form vertical channels on opposite sides of trench (80). Layers (86, 90) have a lateral thickness (88) of the undercut sidewalls (444) and rims (447) spacers. Conductor (94) contacts the N-source and P-body layers, and enhanced P+ region in trench (80).