Interpoly dielectric structure in eeprom device

Abstract

A dielectric insulating composite for insulating a floating gate from a control gate in a nonvolatile memory cell such as EPROM, EEPROM and flash EPROM cells is provided which includes a bottom layer of silicon dioxide formed on the floating gate, a layer of silicon nitride formed on the bottom silicon dioxide layer and a top silicon dioxide layer formed on the nitride layer where the silicon nitride layer has a thickness in the resulting composite which is less than the bottom and top silicon dioxide layers. In one embodiment, the nonvolatile memory cell includes a first conductivity-type semiconductor substrate, source and drain regions formed on a surface of the substrate, an insulating layer thermally grown on top of the source and drain regions, a floating gate positioned on the insulating layer for insulating the floating gate from the source and drain regions, the dielectric insulating composite being positioned between the floating gate and a control gate.