The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 1996
Filed:
Nov. 17, 1994
Tetsuo Kitabayashi, Fukuoka, JP;
Atsushi Obara, Fukuoka, JP;
Jun Miyagi, Fukuoka, JP;
Yasumi Sago, Tokyo, JP;
Masami Sasaki, Tokyo, JP;
Toto Ltd., Fukuoka, JP;
Anelva Co., Tokyo, JP;
Abstract
An electrostatic chuck for electrostatically clamping a semiconductor wafer while minimizing any plane temperature difference thereof has a dielectric layer joined to a metal plate and an inner electrode disposed in the di-electric layer. The dielectric layer has a raised outer rim disposed on an upper surface thereof along an outer peripheral edge thereof, and a plurality of protrusions disposed on the upper surface radially inwardly of the outer rim, the protrusions having upper surfaces for clamping the semiconductor wafer in direct contact therewith. The volume resistivity of the dielectric layer is 10.sup.9 .OMEGA.m or less, and Rmax (maximum height) of the clamping surfaces of the protrusions 5 is 2.0 .mu.m or less and or Ra (center-line average roughness) thereof is 0.25 .mu.m or less. The ratio of the total area of the clamping surfaces of the protrusions to the entire area of the upper surface of the dielectric layer is equal to or greater than 1% and less than 10%.