The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 1995

Filed:

Mar. 14, 1995
Applicant:
Inventors:

Jahanshir J Javanifard, Sacramento, CA (US);

Albert Fazio, Los Gatos, CA (US);

Robert E Larsen, Shingle Springs, CA (US);

James Brennan, Jr, Saratoga, CA (US);

Kerry D Tedrow, Orangevale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518518 ; 365226 ; 36523006 ;
Abstract

An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.


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Javanifard, Jahanshir. (1995). Method and apparatus for controlling the output current provided by a (U.S. Patent No. 5455794). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5455794

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