The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 1995
Filed:
Apr. 08, 1994
Ming-Tsung Liu, Hsin-chu, TW;
Jeffrey Wang, Chang-fa, TW;
Wen Yang Chen, Hsin-chu, TW;
D Y Wu, Hsin-chu, TW;
United Microelectronics Corporation, Hsinchu, TW;
Abstract
A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via A first silicon oxide layer is deposited over the metal layer. This is covered with a spin-on-glass layer. This layer is dried by baking. The spin-on-glass layer is now fully cured. The cured spin-on-glass layer is now ion implanted under the conditions of between about 1E15 to 1E17 atoms/cm.sup.2 and energy between about 50 to 100 KeV. A silicon oxide layer is deposited thereover. Via openings are now made through the silicon oxide layers and the spin-on-glass layer and filled with metal. This results in excellent planarity with no poisoned via problems. Most importantly, this method can be used for submicron technologies having conductor lines which are spaced from one another by submicron feature size and can be processed without the use of an etch-back process for the cured spin on and glass layer.