The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 1995

Filed:

Jan. 25, 1994
Applicant:
Inventors:

Semyon Sherstinsky, San Francisco, CA (US);

Mei Chang, Cupertino, CA (US);

Charles C Harris, Los Gatos, CA (US);

Alan F Morrison, San Jose, CA (US);

Virendra V Rana, Los Gatos, CA (US);

James F Roberts, Austin, TX (US);

Ashok K Sinha, Palo Alto, CA (US);

Simon Tam, Militas, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
F28F / ; C23C / ;
U.S. Cl.
CPC ...
165 802 ; 165 801 ; 1187281 ; 2692 / ; 269903 ;
Abstract

A compound clamp ring secures a semiconductor wafer having a wafer flat portion to a wafer pedestal during wafer processing while maintaining a continuous seal between the wafer edges and the wafer pedestal to prevent leakage of coolant gases circulated at the backside of the wafer into the process environment. The clamp ring has an annular wafer clamp surface adapted to press a round portion of the wafer into sealing abutment with the wafer pedestal. A cavity formed in the clamp ring securely receives a comb-like array of resilient flexures that are adapted to apply a yieldable bias to the flat portion of the wafer to complete the seal between the wafer and the pedestal at the flat portion of the wafer; and encloses the flexures to shield the flexures from process gases.


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