The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 1995
Filed:
Aug. 10, 1992
Chue-San Yoo, Taipei, TW;
Ting-Hwang Lin, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Hsinchu, TW;
Abstract
A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which provides a peeling-free metal silicide gate electrode devices. The process uses annealing of the gate oxide, the polysilicon layer and the metal silicide layer using a rapid thermal annealing process at a temperature more than about 1000.degree. C. and for a time of between about 30 to 60 seconds. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer. Driving in the pattern of lightly doped regions is accomplished by rapid thermal annealing at a temperature of more than about 1000.degree. C. and for a time of between about 30 to 60 seconds with the metal silicide layer having no covering thereover. Heavily doped regions are now formed in the substrate to produce the lightly doped drain under the spacer structure of an MOS FET device. A passivation layer is formed over the structures and electrical connecting structures thereover.