The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 1994

Filed:

Apr. 14, 1993
Applicant:
Inventors:

Robert C Marrs, Scottsdale, AZ (US);

Tadashi Hirakawa, Osaka, JP;

Assignees:

Amkor Electronics, Inc., Paoli, PA (US);

Teijin Limited, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K / ; H01L / ;
U.S. Cl.
CPC ...
361760 ; 174 522 ; 174260 ; 174266 ; 174 524 ; 257687 ; 257787 ; 361730 ; 361736 ; 361761 ; 361777 ; 29841 ;
Abstract

A ball grid array is formed by mounting and electrically connecting one or more electronic devices to a substrate in which vias are formed to interconnect electrically conductive traces formed in a surface of the substrate to solder ball pads formed at an opposite surface of the substrate. The vias are formed by mechanical or laser drilling. Solder balls are formed on each of the pads and are reflow-attached to, for instance, a printed circuit board. The electronic components can include one or more integrated circuit chips, as well as passive components. The electronic components are attached to the substrate using wirebonding, TAB or flip chip connection. An encapsulating material is applied to encapsulate the electronic devices.

Published as:
US5355283A; JPH0774281A; JP3111134B2;

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