The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 1994

Filed:

Mar. 22, 1993
Applicant:
Inventors:

Hitoshi Yokono, Toride, JP;

Hideo Arima, Yokohama, JP;

Takashi Inoue, Yokohama, JP;

Naoya Kitamura, Yokohama, JP;

Haruhiko Matsuyama, Hiratsuka, JP;

Hitoshi Oka, Yokohama, JP;

Fumio Kataoka, Yokohama, JP;

Fusaji Shoji, Yokohama, JP;

Hideyasu Murooka, Yokohama, JP;

Masayuki Kyooi, Yokohama, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
I05K / ;
U.S. Cl.
CPC ...
174264 ; 174250 ; 174256 ; 174262 ; 174265 ; 361792 ; 428901 ;
Abstract

Described herein are interconnected mutilayer boards and their fabrication processes. Multilayer conductor lines of a skeleton structure are formed by conducting multilayer metallization while including all resist layers and metallic under-conductive layers and then removing the resist layers and metallic under-conductive layers at once. Spaces between the multilayer conductor lines of the skeleton structure are then filled with a solventless varnish so that insulating layers are formed. Modules making use of such interconnected multilayer boards and computers having such modules are also described.


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