The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 1994

Filed:

Dec. 26, 1991
Applicant:
Inventors:

Kyuhwan Shim, Daejeon, KR;

Chulsoon Park, Daejeon, KR;

Dojin Kim, Daejeon, KR;

Sungjae Maeng, Daejeon, KR;

Jeonwook Yang, Daejeon, KR;

Youngkyu Choi, Daejeon, KR;

Jinyeong Kang, Daejeon, KR;

Kyungho Lee, Daejeon, KR;

Jinhee Lee, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 39 ; 437176 ; 437184 ;
Abstract

A manufacturing method of GaAs metal semiconductor FET is disclosed. The method comprises the steps of: preparing a GaAs substrate; depositing a silicon layer on the GaAs substrate; forming a first photoresist pattern on the silicon layer by means of well-known image reversal process; etching the silicon layer by means of photolithographic process using the first photoresist pattern as a mask to define ohmic contact regions of source/drain electrodes; forming a second photoresist pattern on the GaAs substrate after removal of the first photoresist pattern to define a channel region; injecting a predetermined quantity of silicon ions into the GaAs substrate to form the channel region; depositing a protective layer around the GaAs substrate after removal of the second photoresist pattern; annealing the substrate deposited with the protective layer to activate silicon ions of the remaining silicon layer and thus diffusing the activating silicon ions into the depth direction of the substrate; forming ohmic contacts on the substrate using an ohmic contact mask after removal of the protective layer and the remaining silicon layer; and forming a gate electrode by using a gate mask.


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