The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 1994

Filed:

Apr. 30, 1992
Applicant:
Inventors:

John Cain, Schertz, TX (US);

Felix Fujishiro, San Antonio, TX (US);

Chang-Ou Lee, San Antonio, TX (US);

Sigmund Koenigseder, San Antonio, TX (US);

Landon Vines, San Antonio, TX (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C23C / ;
U.S. Cl.
CPC ...
427 96 ; 427 97 ; 427 99 ; 427574 ; 427579 ;
Abstract

A semiconductor processing method provides for plasma-enhanced chemical-vapor deposition (PECVD) for intermetal dielectrics while minimizing risk of gate oxide impairment due to plasma discharge. A protective oxide sublayer is deposited without using high-power PECVD. The protective sublayer can be deposited by using chemical-vapor deposition (CVD) without plasma enhancement or by a lower-power PECVD. In the latter case, the initial rf power of the plasma is selected to be low enough to ensure that the gate oxide is not breached in the event of a plasma discharge. The protective sublayer can be thick enough to maintain its integrity in the event of a plasma discharge even during a higher-power PECVD deposition.


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