The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 12, 1993
Filed:
Apr. 15, 1992
Ryozo Nakayama, Yokohama, JP;
Riichiro Shirota, Kawasaki, JP;
Yasuo Itoh, Kawasaki, JP;
Ryouhei Kirisawa, Yokohama, JP;
Hideko Odaira, Tokyo, JP;
Masaki Momodomi, Yokohama, JP;
Yoshihisa Iwata, Yokohama, JP;
Tomoharu Tanaka, Yokohama, JP;
Seiichi Aritome, Kawasaki, JP;
Tetsuo Endoh, Yokohama, JP;
Fujio Masuoka, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.