Process for forming a via in an integrated circuit structure by etching

Abstract

An improved process is described for forming one or more vias through an insulation layer by plasma etching to an underlying metal layer without depositing etch residues, including metal sputtered from the underlying metal layer, onto the sidewalls of the vias, which comprises, in one embodiment, using in the gaseous etchant one or more 3-6 carbon fluorinated hydrocarbons having the formula C.sub.x H.sub.y F.sub.z, wherein x is 3 to 6, y is 0 to 3, and z is 2x-y when the fluorinated hydrocarbon is cyclic and z is 2x-y+2 when the fluorinated hydrocarbon is noncyclic. One or more other fluorine-containing gases may also be used as long as the 3-6 carbon fluorinated hydrocarbons comprise at least 10 volume % of the fluorine-containing gas mixture. The fluorinated hydrocarbon gas or fluorine-containing gas mixture also may be mixed with up to 90 volume % total of one or more inert gases to control the taper of the via walls. At least about 5 sccm of the total gas flow must comprise a 3-6 carbon fluorinated hydrocarbon gas, regardless of the volume % of 3-6 carbon fluorinated hydrocarbon gas in the total gas stream flow. In another embodiment, a controlled amount of one or more nitrogen-containing gases are used with one or more fluorine-containing etchant gas wherein the amount of nitrogen-containing gas ranges from about 1 volume part nitrogen-containing gas per 15 volume parts fluorine-containing gas to about 1 volume part nitrogen-containing gas per 2 volume parts fluorine-containing gas.