The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 1990

Filed:

Mar. 14, 1989
Applicant:
Inventors:

Pierre Merenda, Aix en Provence, FR;

Philippe Chantraine, Neuilly sur Seine, FR;

Daniel Lambert, Juvisy sur Orge, FR;

Assignee:

Bull S.A., Paris, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; B44C / ; C03C / ;
U.S. Cl.
CPC ...
437190 ; 437189 ; 437194 ; 437195 ; 437231 ; 156643 ; 427 51 ; 427 96 ;
Abstract

In a high-density integrated circuit having a multilayered metal interconnection network, a planarization layer is formed over a lower metal layer which includes conductors having steep edges by chemically depositing a dielectric layer in the vapor phase over the lower metal layer so as to fill up hollows formed in the dielectric layer in intervals between the conductors, spreading a viscous layer of spin-on-glass over the dielectric layer, annealing the spin-on-glass layer to form a compact mass, forming vias through the spin-on-glass and dielectric layers to the conductors, and applying an upper metal layer over the spin-on-glass layer so as to fill the vias and provide electrical contacts to the conductors of the lower metal layer.


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