The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 1989

Filed:

Oct. 26, 1988
Applicant:
Inventors:

David N Wang, Cupertino, CA (US);

John M White, Hayward, CA (US);

Kam S Law, Union City, CA (US);

Cissy Leung, Union City, CA (US);

Salvador P Umotoy, Pittsburg, CA (US);

Kenneth S Collins, San Jose, CA (US);

John A Adamik, San Ramon, CA (US);

Ilya Perlov, Mountain View, CA (US);

Dan Maydan, Los Altos Hills, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B44C / ; C03C / ; C03C / ;
U.S. Cl.
CPC ...
156643 ; 118 501 ; 118620 ; 118728 ; 156646 ; 156653 ; 156657 ; 156345 ; 20419212 ; 20419237 ; 204298 ; 427 38 ; 4272481 ; 427294 ;
Abstract

A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either along or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

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