The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 1989
Filed:
Jun. 08, 1987
Lawrence H Lin, Alamo, CA (US);
Daniel L Cavan, Woodside, CA (US);
Robert B Howe, San Jose, CA (US);
Insystems, Inc., San Jose, CA (US);
Abstract
An inspection system (10, 100) employs a Fourier transform lens (34, 120) and an inverse Fourier transform lens (54, 142) positioned along an optic axis (48, 144) to produce from an illuminated area of a patterned specimen wafer (12) a spatial frequency spectrum whose frequency components can be selectively filtered to produce an image pattern of defects in the illuminated area of the wafer. Depending on the optical component configuration of the inspection system, the filtering can be accomplished by a spatial filter of either the transmissive (50) or reflective (102) type. The lenses collect light diffracted by a wafer die (14) aligned with the optic axis and light diffracted by other wafer dies proximately located to such die. The inspection system is useful for inspecting only dies having many redundant circuit patterns. The filtered image strikes the surface of a two-dimensional photodetector array (58) which detects the presence of light corresponding to defects in only the illuminated on-axis wafer die. Inspection of all possible defects in the portions of the wafer surface having many redundant circuit patterns is accomplished by mounting the wafer onto a two-dimensional translation stage and moving the stage (40) so that the illuminated area continuously scans across the wafer surface from die to die until the desired portions of the wafer surface have been illuminated. The use of a time delay integration technique permits continuous stage movement and inspection of the wafer surface in a raster scan fashion.