The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 1988
Filed:
Jun. 03, 1986
Applicant:
Inventors:
John K Chu, Fremont, CA (US);
Sanjiv K Mittal, Fremont, CA (US);
John T Orton, Pleasanton, CA (US);
Jagir S Multani, Fremont, CA (US);
Robert Jecmen, Pleasanton, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B05D / ; B05D / ;
U.S. Cl.
CPC ...
427 38 ; 156646 ; 156653 ; 427 96 ; 427 99 ; 427255 ; 4272553 ; 437228 ; 437231 ; 437235 ; 437245 ;
Abstract
A planarization process for a double metal very large scale integration (VLSI) technology is disclosed. To compensate for an irregular surface topology encountered in a dielectric medium between the two metals, a CVD dielectric layer and a glass layer are first deposited above the first metal. Then an etch-back process is used to uniformly etch back the CVD dielectric and the glass layers at the same rate, leaving a planarized surface for subsequent deposition of a second dielectric layer and a second metal layer.