The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Jun. 14, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Li-Ling Su, Hsinchu, TW;

Ming-Hsien Lin, Hsinchu, TW;

Hsin-Ping Chen, Hsinchu, TW;

Shao-Kuan Lee, Hsinchu, TW;

Cheng-Chin Lee, Hsinchu, TW;

Yen-Ju Wu, Hsinchu, TW;

Hsin-Yen Huang, Hsinchu, TW;

Hsi-Wen Tien, Hsinchu, TW;

Chih-Wei Lu, Hsinchu, TW;

Chia-Chen Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/00 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10W 20/097 (2026.01); H10W 20/076 (2026.01); H10W 20/084 (2026.01); H10W 20/42 (2026.01);
Abstract

A semiconductor device includes a substrate, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. The heat dissipation dielectric layer is disposed on the substrate and has a thermal conductivity greater than 10 W/mK. The conductive interconnect structure is disposed in the heat dissipation dielectric layer. The blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.


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Su, Li-Ling. (2026). Interconnect layer and method for manufacturing the same (U.S. Patent No. 12796427). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796427

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