The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Aug. 30, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Julien Frougier, Albany, NY (US);

Chanro Park, Clifton Park, NY (US);

Min Gyu Sung, Latham, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01); H10D 86/00 (2025.01); H10W 20/00 (2026.01); H10W 20/40 (2026.01); H10D 30/43 (2025.01); H10W 20/41 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6729 (2025.01); H10D 30/014 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01); H10D 84/0149 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01); H10D 86/00 (2025.01); H10W 20/069 (2026.01); H10W 20/0696 (2026.01); H10W 20/481 (2026.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10W 20/082 (2026.01); H10W 20/094 (2026.01); H10W 20/427 (2026.01);
Abstract

Backside self-aligned contact designs using a replacement contact process with unique placeholder profile are provided. In one aspect, a semiconductor device includes: a field-effect transistor(s) on a frontside of the device; backside power rails on a backside of the device; a backside source/drain region contact connecting a given one of the backside power rails to a source/drain region of the field-effect transistor(s), and a dielectric placeholder(s) between the given backside power rail and another source/drain region of the field-effect transistor(s), where a first end of the dielectric placeholder(s) having a width Wdirectly contacts the given backside power rail, a second end of the dielectric placeholder(s) having a width Wdirectly contacts the other source/drain region, where W>W. The field-effect transistor(s) can include a stack of active layers with bottom dielectric isolation, and a gate-all-around configuration. A method of fabricating the present semiconductor devices is also provided.


Find Patent Forward Citations

Quick Actions:

Xie, Ruilong. (2026). Placeholder profile for backside self-aligned contact (U.S. Patent No. 12795994). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12795994

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