The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Apr. 17, 2023
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Navneet K. Jain, Milpitas, CA (US);

David Charles Pritchard, Schenectady, NY (US);

Romain H.A. Feuillette, Williston, VT (US);

James P. Mazza, Saratoga Springs, NY (US);

Hong Yu, Clifton Park, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/01 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6211 (2025.01); H10D 30/024 (2025.01); H10D 62/292 (2025.01); H10D 64/01326 (2026.01); H10D 64/017 (2025.01); H10D 64/671 (2025.01); H10D 84/0128 (2025.01); H10D 84/0135 (2025.01); H10D 84/0151 (2025.01); H10D 84/0188 (2025.01);
Abstract

Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.


Find Patent Forward Citations

Quick Actions:

Jain, Navneet. (2026). Multi-fin fin-type field effect transistor with fine-tuned effective channel width (U.S. Patent No. 12795982). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12795982

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…