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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12787429 B1

PDFFull Text
Date of Patent:
Nov. 03, 2026

Filed:

Dec. 06, 2023

Lateral passive diodes co-integrated with nanosheet technology

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Shahrukh Khan, Sandy Hook, CT (US);

Biswanath Senapati, Mechanicville, NY (US);

Utkarsh Bajpai, Delmar, NY (US);

Chen Zhang, Santa Clara, CA (US);

Huimei Zhou, Albany, NY (US);

Junli Wang, Slingerlands, NY (US);

Jay William Strane, Wappingers Falls, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Scully, Scott, Murphy & Presser, P.C.

Samuel Waldbaum

Primary Examiner:

Vu A Vu

Int. Cl.
CPC ...
H01L 21/66 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01); H10W 20/41 (2026.01);
U.S. Cl.
CPC ...
H10D 84/856 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 88/01 (2025.01); H10W 20/427 (2026.01);
Abstract

A semiconductor structure is provided that includes a lateral passive diode co-integrated with nanosheet stacked FET technology. Notably, the semiconductor structure includes a passive/diode device region including a lateral passive diode that is located between two nanosheet stacks. In embodiments, a logic device region including a stacked nanosheet transistor is located adjacent to the passive/diode device region.

Find Patent Forward Citations

Quick Actions:

Khan, Shahrukh. (2026). Lateral passive diodes co-integrated with nanosheet technology (U.S. Patent No. 12787429). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787429

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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