The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Jul. 26, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yi-Hsin Nien, Hsinchu, TW;

Chih-Yu Lin, Hsinchu, TW;

Hidehiro Fujiwara, Hsinchu, TW;

Yen-Huei Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/412 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/412 (2013.01); H10B 10/12 (2023.02);
Abstract

A memory circuit includes a memory array comprising a plurality of memory cells. The memory circuit includes a first pre-charge circuit coupled to at least one access line electrically connected to the plurality of memory cells and configured to be in a first state during a standby mode of the memory array. The memory circuit includes a second pre-charge circuit coupled to the at least one access line and configured to be in a second state during the standby mode.


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Nien, Yi-Hsin. (2026). Systems and methods to mitigate cycle time degradation by nbti effect on pdp sram (U.S. Patent No. 12784821). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12784821

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