The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Feb. 22, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chen-Hsuan Tsai, Taitung City, TW;

Yu-Lin Chiang, Hsinchu, TW;

Chin-Chuan Chang, Hsinchu County, TW;

Ying-Ching Shih, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 70/69 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 72/90 (2026.01); H10W 74/00 (2026.01); H10W 74/40 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 70/69 (2026.01); H10W 74/012 (2026.01); H10W 74/016 (2026.01); H10W 74/117 (2026.01); H10W 74/121 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 70/60 (2026.01); H10W 72/07232 (2026.01); H10W 72/07332 (2026.01); H10W 72/07352 (2026.01); H10W 72/07353 (2026.01); H10W 72/321 (2026.01); H10W 72/334 (2026.01); H10W 72/934 (2026.01); H10W 72/953 (2026.01); H10W 74/00 (2026.01); H10W 74/10 (2026.01); H10W 74/40 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 80/334 (2026.01); H10W 80/721 (2026.01); H10W 80/732 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01); H10W 90/794 (2026.01);
Abstract

A package structure includes a first redistribution circuit structure, a first semiconductor die, and a second semiconductor die. The first redistribution circuit structure has a first side and a second side opposite to the first side. The first semiconductor die is disposed over the firs side of the first redistribution circuit structure. The second semiconductor die is disposed over the second side of the first redistribution circuit structure and is electrically connected thereto, where the second semiconductor die includes a substrate, an interconnect structure disposed on the substrate, a plurality of conductive terminals disposed on and electrically connected to the interconnect structure, and a dielectric layer disposed on the interconnect structure and laterally covering the plurality of conductive terminals. A material of the dielectric layer included in the second semiconductor die is different from a material of a dielectric layer included in the first redistribution circuit structure.


Find Patent Forward Citations

Quick Actions:

Tsai, Chen-Hsuan. (2026). Package structure with connecting structure and manufacturing method thereof (U.S. Patent No. 12777951). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12777951

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