The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Mar. 20, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chao-Kai Chan, Taichung City, TW;

Chung-Hao Tsai, Changhua County, TW;

Chuei-Tang Wang, Taichung City, TW;

Wei-Ting Chen, Tainan City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 20/41 (2026.01); H10D 1/66 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10W 20/435 (2026.01); H10D 1/665 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 84/0128 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10W 20/42 (2026.01);
Abstract

A method of forming a semiconductor device is provided. A transistor is formed at a first side of the substrate and a first dielectric layer is formed aside the transistor. A first metal via is formed through the first dielectric layer and aside the transistor. A first interconnect structure is formed over the first side of the substrate and electrically connected to the transistor and the first metal via. The substrate is thinned from a second side of the substrate. A capacitor is formed at the second side of the substrate and a second dielectric layer is formed aside the capacitor. A second metal via is formed through the second dielectric layer and the substrate and electrically connected to the first metal via.


Find Patent Forward Citations

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Chan, Chao-Kai. (2026). Methods of forming semiconductor devices including a capacitor and front and backside interconnect structures (U.S. Patent No. 12777915). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12777915

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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