The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Feb. 16, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Ting Lai, Hsinchu City, TW;

Hsin-Yu Pan, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/09 (2026.01); H10P 72/70 (2026.01); H10W 20/20 (2026.01); H10W 20/42 (2026.01); H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 72/00 (2026.01); H10W 74/01 (2026.01); H10W 90/00 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01);
U.S. Cl.
CPC ...
H10W 70/09 (2026.01); H10P 72/74 (2026.01); H10W 20/20 (2026.01); H10W 20/42 (2026.01); H10W 70/60 (2026.01); H10W 70/614 (2026.01); H10W 70/635 (2026.01); H10W 72/0198 (2026.01); H10W 74/019 (2026.01); H10W 90/00 (2026.01); H10P 72/7424 (2026.01); H10W 72/241 (2026.01); H10W 72/874 (2026.01); H10W 72/9413 (2026.01);
Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a stack of composite conductive structures disposed on the first redistribution structure, and an insulating encapsulation disposed on the first redistribution structure and laterally covering the semiconductor die and the stack of composite conductive structures. The stack of composite conductive structures includes a lower tier and an upper tier stacked upon the lower tier. Each of the lower tier and the upper tier includes a support layer, through material vias (TMVs) penetrating through the support layer, and a conductive adhesive member underlying the support layer and the TMVs.


Find Patent Forward Citations

Lai, Chih-Ting. (2026). Semiconductor package and manufacturing method thereof (U.S. Patent No. 12765395). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12765395

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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