The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Aug. 25, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shih-Cheng Chen, Hsinchu, TW;

Jung-Hung Chang, Hsinchu, TW;

Chien Ning Yao, Hsinchu, TW;

Tsung-Han Chuang, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/017 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/018 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

A device includes: a stack of semiconductor channels; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; a source/drain contact on the source/drain region; and a gate spacer between the source/drain contact and the gate structure. The gate spacer includes: a first spacer layer in contact with the gate structure; and a second spacer layer between the first spacer layer and the source/drain contact, the second spacer layer having a first portion on the stack and a second portion on the first portion, the second portion being thinner than the first portion.


Find Patent Forward Citations

Chen, Shih-Cheng. (2026). Field effect transistor with narrowed spacer and method (U.S. Patent No. 12765029). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12765029

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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