The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Apr. 16, 2024
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

He Ren, San Jose, CA (US);

Raman Gaire, Mechanicville, NY (US);

Shi You, San Jose, CA (US);

Pranav Ramesh, Mountain View, CA (US);

Houssam Lazkani, Schenectady, NY (US);

Shawn Thomas, Chesterfield, MO (US);

Abhishek Dube, Fremont, CA (US);

Mehul B. Naik, San Jose, CA (US);

Songkram Sonny Srivathanakul, Waterford, NY (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); C30B 25/18 (2006.01); C30B 29/06 (2006.01); C30B 29/68 (2006.01); H10W 20/00 (2026.01);
U.S. Cl.
CPC ...
H10D 64/0112 (2026.01); C30B 25/18 (2013.01); C30B 29/06 (2013.01); C30B 29/68 (2013.01); H10D 64/01 (2025.01); H10W 20/01 (2026.01);
Abstract

Semiconductor devices and methods for manufacturing the same are provided. The method includes epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region of a semiconductor layer. The trench is formed in the semiconductor layer and the trench exposes the source/drain feature. The method further includes epitaxially growing an undoped crystalline silicon-containing capping layer over the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer over the doped silicon-containing amorphous layer. The method further includes selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer. The method further includes removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.


Find Patent Forward Citations

Ren, He. (2026). Low-temperature selective epitaxy contact approach (U.S. Patent No. 12765027). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12765027

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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