Semiconductor device including a multiple-time programmable memory cell

Abstract

A semiconductor device includes a non-volatile memory structure. A layout of metallization layers in the semiconductor device coupled with the non-volatile memory structure is configured to achieve a low likelihood of electromigration in the non-volatile memory structure, particularly at operating temperature parameters associated with demanding applications such as automotive and/or industrial, among other examples. The non-volatile memory structure is electrically coupled with a first metallization layer. The first metallization layer electrically couples the non-volatile memory structure with a second metallization layer that is configured as a write bit line metallization layer for the non-volatile memory structure. The first metallization layer electrically couples the non-volatile memory structure with a third metallization layer above the second metallization layer. The third metallization layer is configured as a read bit line metallization layer for the non-volatile memory structure.