The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2026
Filed:
Jun. 03, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Shih-Wei Peng, Hsinchu, TW;
Chih-Min Hsiao, Hsinchu, TW;
Chien-Wen Lai, Hsinchu, TW;
Jiann-Tyng Tzeng, Hsinchu, TW;
Yu-Luen Deng, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
Provided is a method for manufacturing integrated circuit (IC) devices including the operations of forming a first metal pattern (Mx) on a semiconductor substrate, forming a first via pattern (Vx) on the first metal pattern using an area selective deposition (ASD) that includes first and second vias formed adjacent opposed edges or terminal portions of the first metal pattern, and forming a second metal pattern (Mx+1) on the first via pattern with substantially no pattern overlap to form a zero enclosure and wherein a pair of adjacent vias are separated by a distance corresponding to the smallest end-to-end metal pattern spacing permitted under a set of design rules applied during the design of the IC devices.