The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Oct. 18, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chin-Lung Chung, Hsinchu, TW;

Shin-Yi Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H10W 20/00 (2026.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01); H10W 20/44 (2026.01); H10W 20/47 (2026.01);
U.S. Cl.
CPC ...
H10W 20/055 (2026.01); H10W 20/034 (2026.01); H10W 20/035 (2026.01); H10W 20/038 (2026.01); H10W 20/056 (2026.01); H10W 20/075 (2026.01); H10W 20/077 (2026.01); H10W 20/082 (2026.01); H10W 20/42 (2026.01); H10W 20/425 (2026.01); H10W 20/4407 (2026.01); H10W 20/4424 (2026.01); H10W 20/4435 (2026.01); H10W 20/4446 (2026.01); H10W 20/47 (2026.01);
Abstract

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes the following steps. A trench is formed in a first interlayer dielectric (ILD) layer. A metal conductor with metal dopants is filled in the trench. Planarization is performed on the metal conductor with the metal dopants. A thermal treatment, a photo treatment or a bias-assist treatment is performed on the metal conductor with the metal dopants to form a self-forming metal capping layer on a first metal layer. An etching stop bi-layer structure is formed on the first interlayer dielectric layer and the self-forming metal capping layer. A via, a second interlayer dielectric (ILD) layer and a second metal layer are formed on the etching stop bi-layer structure. The via is embedded in the second interlayer dielectric layer and the via is disposed between the first metal layer and the second metal layer.


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