The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Nov. 27, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shen-Yang Lee, Hsinchu, TW;

Hsiang-Pi Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

A method for manufacturing a semiconductor device includes: forming a channel portion which includes a semiconductor material; sequentially forming a first oxide film and a second oxide film on the channel portion, the first oxide film and the second oxide film being made of different materials, one of the first oxide film and the second oxide film including a rare-earth metal; performing a treatment such that the first oxide film and the second oxide film are formed into an interfacial layer which includes a first dielectric material and which is formed on the channel portion; forming a gate dielectric layer which includes a second dielectric material and which is formed on the interfacial layer, the second dielectric material being different from the first dielectric material; and forming a gate electrode on the gate dielectric layer.


Find Patent Forward Citations

Lee, Shen-Yang. (2026). Semiconductor device including interfacial layer with cet scaling and method for manufacturing the same (U.S. Patent No. 12751047). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12751047

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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