The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Dec. 22, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Carl H. Naylor, Portland, OR (US);

Kirby Maxey, Hillsboro, OR (US);

Chelsey Dorow, Portland, OR (US);

Sudarat Lee, Hillsboro, OR (US);

Kevin O'brien, Portland, OR (US);

Ashish V. Penumatcha, Beaverton, OR (US);

Scott B. Clendenning, Portland, OR (US);

Uygar Avci, Portland, OR (US);

Matthew Metz, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 62/80 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6757 (2025.01); H10D 99/00 (2025.01); H10D 30/6739 (2025.01); H10D 30/6755 (2025.01); H10D 62/80 (2025.01);
Abstract

A metal chalcogenide material layer of lower quality provides a transition between a metal chalcogenide material layer of higher quality and a gate insulator material that separates the metal chalcogenide material layers from a gate electrode of a metal-oxide semiconductor field effect transistor (MOSFET) structure. Gate insulator material may be more readily initiated and/or or precisely controlled to a particular thickness when formed on lower quality metal chalcogenide material. Accordingly, such a material stack may be integrated into a variety of transistor structures, including multi-gate, multi-channel nanowire or nanosheet transistor structures.


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