The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Jun. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Ling Chung, Hsinchu, TW;

Chun-Chih Cheng, Changhua, TW;

Ying-Liang Chuang, Hsinchu, TW;

Ming-Hsi Yeh, Hsinchu, TW;

Kuo-Bin Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10P 14/44 (2026.01); H10W 20/00 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 64/01316 (2026.01); H10D 64/017 (2025.01); H10D 64/666 (2025.01); H10D 84/0137 (2025.01); H10D 84/038 (2025.01); H10P 14/44 (2026.01); H10W 20/056 (2026.01); H10W 20/077 (2026.01); H10W 20/081 (2026.01); H10W 20/42 (2026.01);
Abstract

Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; a tungsten (W) cap formed from W material deposited over the metal gate and between the gate spacers; and a via gate (VG) formed above the W cap. A semiconductor fabrication method includes: receiving a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; depositing tungsten (W) material over the substrate; removing unwanted W material to form a W cap; and forming a via gate (VG) on the W cap.


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