The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Dec. 03, 2024
Applicant:

Peking University, Beijing, CN;

Inventors:

Yimao Cai, Beijing, CN;

Zongwei Wang, Beijing, CN;

Gaoqi Yang, Beijing, CN;

Shengyu Bao, Beijing, CN;

Ru Huang, Beijing, CN;

Assignee:

PEKING UNIVERSITY, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); H10B 63/30 (2023.02); H10B 63/84 (2023.02); H10N 70/023 (2023.02);
Abstract

The present disclosure provides a three-dimensional memory array and a preparation method thereof, wherein the three-dimensional memory array includes memory cells arranged in an array; wherein in each memory cell: one end of the memory cell is connected to a word line WL, and the other end thereof is connected to a bit line BL; a corresponding gating transistor is arranged at the bottom of each word line WL, and the bottom of the word line WL is connected to the drain of the gating transistor; the gate of the gating transistor is connected to a gate line GL, and the source of the gating transistor is connected to a source line SL; the bit line BL, the word line WL, the source line SL and the gate line GL control the state of the memory cell.


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