The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Feb. 05, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jun Kyoung Lee, Suwon-si, KR;

Tae Seong Kim, Suwon-si, KR;

Ho-Jin Lee, Suwon-si, KR;

Dong-Chan Lim, Suwon-si, KR;

Jae Won Hwang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H10W 72/00 (2026.01); H10W 72/90 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10F 39/807 (2025.01); H10F 39/8063 (2025.01); H10F 39/809 (2025.01); H10F 39/811 (2025.01); H10W 72/01938 (2026.01); H10W 72/01953 (2026.01); H10W 72/952 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/792 (2026.01);
Abstract

The present disclosure provides a semiconductor device manufacturing method that includes forming a lower chip and an upper chip, and bonding the lower chip and the upper chip to each other. The forming of the lower chip includes providing a lower substrate, sequentially forming a lower interlayer insulating film and a pre-lower adhesive film, etching portions of the pre-lower adhesive film and the lower interlayer insulating film to form a lower trench, forming, using a sputtering process, a first lower seed film and a second lower seed film. The forming of the upper chip includes providing an upper substrate, sequentially forming an upper interlayer insulating film and a pre-upper adhesive film, etching portions of the pre-upper adhesive film and the upper interlayer insulating film to form an upper trench, forming, using the sputtering process, a first upper seed film and a second upper seed film.


Find Patent Forward Citations

Lee, Jun. (2026). Semiconductor device manufacturing method and semiconductor device manufactured using the same (U.S. Patent No. 12740173). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12740173

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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